User manual MATLAB SIMULINK HDL CODER 1

[. . . ] Simulink® HDL CoderTM 1 User's Guide How to Contact The MathWorks Web Newsgroup www. mathworks. com/contact_TS. html Technical Support www. mathworks. com comp. soft-sys. matlab suggest@mathworks. com bugs@mathworks. com doc@mathworks. com service@mathworks. com info@mathworks. com Product enhancement suggestions Bug reports Documentation error reports Order status, license renewals, passcodes Sales, pricing, and general information 508-647-7000 (Phone) 508-647-7001 (Fax) The MathWorks, Inc. 3 Apple Hill Drive Natick, MA 01760-2098 For contact information about worldwide offices, see the MathWorks Web site. Simulink® HDL CoderTM User's Guide © COPYRIGHT 2006­2010 by The MathWorks, Inc. The software described in this document is furnished under a license agreement. The software may be used or copied only under the terms of the license agreement. [. . . ] The coder always creates a generated model as part of the code generation process, and always generates test benches based on the generated model, rather than the original model. In cases where no latency or numeric differences occur, you can disregard the generated model except when generating test benches. The coder also provides options that let you · Suppress display of the generated model. · Create and display the only generated model, with code generation suppressed. 8-2 Overview of Generated Models · Specify the color highlighting of differences between the original and generated models. These options are described in "Defaults and Options for Generated Models" on page 8-12. 8-3 8 Generating Bit-True Cycle-Accurate Models Example: Numeric Differences This example first examines a simple model that uses a code generation control file to select a speed-optimized Sum block implementation. It then examines a generated model and locates the numeric changes introduced by the optimization. If you are not familiar with code generation control files and selection of block implementations, see Chapter 5, "Code Generation Control Files". The model, simplevectorsum, consists of a subsystem, vsum, driven by a vector input of width 10, with a scalar output. The following figure shows the root level of the model. The device under test is the vsum subsystem, shown in the following figure. The subsystem contains a Sum block, configured for vector summation. The model is configured to use a code generation control file, svsumctrl. m. The control file (shown in the following listing) maps the Tree implementation to the Sum block within the vsum subsystem. This implementation, optimized for minimal latency, generates a tree-shaped structure of adders for the Sum block. function config = svsumctrl % Code generation control file for simplevectorsum model. 8-4 Example: Numeric Differences config = hdlnewcontrol(mfilename); % Specify tree-structured adders implementaton for Sum block. 'Tree', {}); The File name field of the Configuration Parameters dialog box (shown in the following figure) specifies that this control file is to be used during code generation. When code generation is initiated, the coder displays messages similar to those shown in the following example. The messages indicate that the control file is applied; control file processing is followed by creation of the generated model and generation of HDL code. ### Applying HDL Code Generation Control Statements 8-5 8 Generating Bit-True Cycle-Accurate Models ### 1 Control Statements to be applied ### Begin Model Generation ### Generating new model: gm_simplevectorsum. mdl ### Model Generation Complete. ### ### ### ### Begin VHDL Code Generation Generating package file hdlsrc\vsum_pkg. vhd Working on simplevectorsum/vsum as hdlsrc\vsum. vhd HDL Code Generation Complete. The generated model, gm_ simplevectorsum, is displayed after code generation. This model is shown in the following figure. At the root level, this model appears identical to the original model, except that the vsum subsystem has been highlighted in cyan. This highlighting indicates that the subsystem differs in some respect from the vsum subsystem of the original model. Observe that the Sum block is now implemented as a subsystem, which is also highlighted. 8-6 Example: Numeric Differences The following figure shows the internal structure of the Sum subsystem. The vector sum is implemented as a tree of adders (Sum blocks). The vector input signal is demultiplexed and connected, as five pairs of operands, to the five leftmost adders. The widths of the adder outputs increase from left to right, as required to avoid overflow in computing intermediate results. A Data Conversion block, inserted before the final output, converts the 20-bit fixed-point result to the int16 data type required by the model. 8-7 8 Generating Bit-True Cycle-Accurate Models Example: Latency This example uses the simplevectorsum_cascade model. This model is identical to the model in the previous example ("Example: Numeric Differences" on page 8-4), except that it uses a control file that selects a cascaded implementation for the Sum block. [. . . ] Property/value pairs are passed in the form 'PropertyName', PropertyValue These property settings determine characteristics of the test bench code. Many of these properties are identical to those for makehdl, while others are specific to test bench generation (for example, options for generation of test bench stimuli). The next section, "Defaults for Test Bench Code Generation" on page 18-30, summarizes the defaults that are specific to generated test bench code. For detailed descriptions of each property and its effect on generated code, see Chapter 16, "Properties -- Alphabetical List", and Chapter 17, "Property Reference". Generating Stimulus and Output Data makehdltb generates test data from signals connected to inputs of the subsystem under test. [. . . ]