User manual TYAN TOMCAT I II

[. . . ] Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2 Hardware Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1. 4 Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] TheTypematic Rate (6, 8, 10, 12, 15, 20, 24, or 30 characters per second) and Typematic Rate Delay (250, 500, 750, or 1000 milliseconds) controls the speed at which the keystroke is repeated. The selected character is displayed when a key is held down after a delay set by the Typematic Rate Delay. It then repeats at a rate set by the Typematic Rate. S1562-001-01 32 w Security Option This category allows you to limit access to the system setup, or just setup. Default value is Setup System The system will not boot and access to Setup will be denied if the correct password is not entered at the prompt Setup The system will boot, but access to setup will be denied if the password is not entered at the prompt w PS/2 Mouse Function Enables or disables PS/2 mouse function. w PCI/VGA Palette Snooping The purpose of this option is to allow multiple VGA devices on different busses in a system to have data written from CPU to each set of palette registers of every video device. w Video BIOS Shadow It determines whether Video BIOS will be copied to RAM, however, it is an optional chipset design. Default is Enabled. 4. 7 Chipset Features Setup This screen controls the settings for the board's chip set. The Chipset Features Screen ROM ISA BIOS CHIPSET SETUP UTILITY AWARD SOFTWARE, INC. DRAM RAS# Precharge Time DRAM R/W Leadoff Timing Fast RAS# To CAS# Delay DRAM Read Burst Timing DRAM Write Burst Timing DRAM Speculative Leadoff Turn-Around Insertion System BIOS Cacheable Video BIOS Cacheable 8 bit I/O Recovery Time 16 bit I/O Recovery Time Memory Hole at 15M/16M IDE Block Mode IDE Primary Master PIO IDE Primary Slave PIO IDE Secondary Master PIO IDE Secondary Slave PIO On-Chip Primary PCI IDE On-Chip Secondary PCI IDE :4 :7/6 :3 :x4444 :x4444 :Disabled :Disabled :Enabled :Enabled :1 :1 :Disabled :Disabled :Auto :Auto :Auto :Auto :Enabled :Enabled PCI Slot IDE 2nd Channel Peer Concurrency Chipset Special Features DRAM ECC/Parity Select Onboard FDC Controller Onboard Serial Port 1 Onboard Serial Port 2 Onboard Parallel Port Parallel Port Mode :Enabled :Disabled :Disabled :Parity :Enabled :Com1/3F8 :Com2/2F8 :378/IRQ7 :Normal ESC :Quit F1 F5 F6 F7 :Select Item :Help PU/PD/+/- :Modify :Old Values (Shift)F2 :Color :Load BIOS Defaults :Load Setup Defaults S1562-001-01 33 w Chipset Features The DRAM timings can be altered from the default to optimize system performance. Be aware though that these settings are sensitive to the type and speed of DRAMs being used and can cause lockups or data lost if set incorrectly. w DRAM RAS# Precharge Time DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data will be lost. w DRAM R/W Leadoff Timing This sets the number of CPU clocks allowed before reads and writes to DRAM are performed. The default of 8/7 would set the leadoff timing for reads to eight clocks and writes to seven clocks. w DRAM RAS to CAS Delay When DRAM is refreshed, both rows and columns are addressed separately. This option allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe(CAS). w DRAM Read/Write Burst Timing This sets the timing for Burst mode reads from DRAM. Burst read and write requests are generated by the CPU in four separate parts. The "x" is the leadoff cycle and is determined by the chipset and the memory timing. The lower the timing numbers, the faster the system will address memory. [. . . ] If it displays a warning message about the CPU mode, you will have to try again. S1562-001-01 58 Once you have satisfied the two requirements mentioned above, you can run FMW. You can copy the contents of the "Flash" directory to your hard drive, or you can run the utility from a backup of the support floppy disk. Make sure the new BIOS file is in the same directory as the FMW utility. To run FMW, change to the "Flash" directory if you are not already in it. [. . . ]