User manual TYAN TOMCAT IIIS D

[. . . ] Revision 1. 0 Single S1563S/Dual S1563D Pentium Class 430 HX 75MHz thru 200MHz PCI-ISA System Board User's Manual Table Of Contents 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2 Hardware Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1. 3 Software Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1. 4 Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Note that the BIOS cannot tell from 720k, 1. 2M or 1. 44M drive type as they are all 80 tracks Disabled BIOS will not search for the type of floppy disk drive by track number. Note that there will not be any warning messages if the drive installed is 360K w Boot Up NumLock Status Default value is On On Off Keypad is number keys Keypad is arrow keys w Memory Parity Check The default value is disabled w Gate A20 Option Gate A20 controls the ability to access memory addresses above 1 MB by enabling (Fast) or disabling (Normal) access to the processor. Default value is Fast w Typematic Rate Setting, Typematic Rate (char/sec), and Typematic Delay. TheTypematic Rate (6, 8, 10, 12, 15, 20, 24, or 30 characters per second) and Typematic Rate Delay (250, 500, 750, or 1000 milliseconds) controls the speed at which the keystroke is repeated. The selected character is displayed when a key is held down after a delay set by the Typematic Rate Delay. It then repeats at a rate set by the Typematic Rate. S1563-001-01 www. tyan. com 33 w Security Option This category allows you to limit access to the system setup, or just setup. Default value is Setup System The system will not boot and access to Setup will be denied if the correct password is not entered at the prompt Setup The system will boot, but access to setup will be denied if the password is not entered at the prompt w PS/2 Mouse Function Enables or disables PS/2 mouse function. w PCI/VGA Palette Snooping The purpose of this option is to allow multiple VGA devices on different busses in a system to have data written from CPU to each set of palette registers of every video device. w Video BIOS Shadow It determines whether Video BIOS will be copied to RAM, however, it is an optional chipset design. Default is Enabled. 4. 7 Chipset Features Setup This screen controls the settings for the board's chip set. The Chipset Features Screen ROM ISA BIOS CHIPSET SETUP UTILITY AWARD SOFTWARE, INC. Auto Configuration DRAM Timing DRAM RAS# Precharge Time DRAM R/W Leadoff Timing Fast RAS# To CAS# Delay DRAM Read Burst Timing DRAM Write Burst Timing Turbo Read Leadoff DRAM Speculative Leadoff Turn-Around Insertion ISA Clock System BIOS Cacheable Video BIOS Cacheable 8 bit I/O Recovery Time 16 bit I/O Recovery Time Memory Hole at 15M/16M Peer Concurrency Chipset Special Features DRAM ECC/Parity Select :Disabled :70ns :4 :7/6 :3 :x4444 :x4444 :Disabled :Disabled :Disabled :PCILK/4 :Enabled :Enabled :1 :1 :Disabled :Enabled :Enabled :Parity Memory Parity/ECC Check Single Bit Error Report L2 Cache Cacheable Size Chipset NA# Asserted Pipline Cache Timing :Disabled :Disabled :64MB :Enabled :Faster ESC :Quit F1 F5 F6 F7 :Select Item :Help PU/PD/+/- :Modify :Old Values (Shift)F2 :Color :Load BIOS Defaults :Load Setup Defaults S1563-001-01 www. tyan. com 34 w Chipset Features The DRAM timings can be altered from the default to optimize system performance. Be aware though that these settings are sensitive to the type and speed of DRAMs being used and can cause lockups or data lost if set incorrectly. w DRAM RAS# Precharge Time DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data will be lost. w DRAM R/W Leadoff Timing This sets the number of CPU clocks allowed before reads and writes to DRAM are performed. The default of 8/7 would set the leadoff timing for reads to eight clocks and writes to seven clocks. w DRAM RAS to CAS Delay When DRAM is refreshed, both rows and columns are addressed separately. This option allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe(CAS). w DRAM Read/Write Burst Timing This sets the timing for Burst mode reads from DRAM. [. . . ] This utility can be downloaded from the factory's BBS(Consult your system vendor for the phone #). The system BIOS is stored on a 'flash' EPROM chip on the mainboard which can be erased and reprogrammed by the FMW. AWDFLASH. EXE AMIFLASH. COM -The Flash Memory Writer utility for Award to Award upgrade. -A text file of instructions -XX-A 2-digit version number. README *S56AWXX. BIN Flash memory writer records (or `programs') a new BIOS onto the flash memory chip. [. . . ]