User manual TYAN TOMCAT IVS D

[. . . ] Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2 Hardware Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 3 Software Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. 1 Unpacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Be aware though that these settings are sensitive to the type and speed of DRAMs being used and can cause lockups or data lost if set incorrectly. w DRAM RAS# Precharge Time DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data will be lost. w DRAM R/W Leadoff Timing This sets the number of CPU clocks allowed before reads and writes to DRAM are performed. The default of 8/7 would set the leadoff timing for reads to eight clocks and writes to seven clocks. w DRAM RAS to CAS Delay When DRAM is refreshed, both rows and columns are addressed separately. This option allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe(CAS). w DRAM Read/Write Burst Timing This sets the timing for Burst mode reads from DRAM. Burst read and write requests are generated by the CPU in four separate parts. The "x" is the leadoff cycle and is determined by the chipset and the memory timing. The lower the timing numbers, the faster the system will address memory. The default for write burst timing is x4444. S1564-001-01 www. tyan. com 34 w Speculative Leadoff The 430HX chipset is capable of allowing a DRAM read request to be generated slightly before the address has been fully decoded. More simply, the CPU will issue a read request and included with this request is the place(address) in memory where the desired data is to be found. When enabled, the controller will issue the read command slightly before it has finished determining the address. w Turn-Around Insertion When this is enabled, the chipset will insert one extra clock to the turn-around of back to back DRAM cycles. w System BIOS Cacheable When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached. When using operating systems that do not access the BIOS (Unix, OS/2, NT, etc. . . ) this setting can be disabled. w Video BIOS Cacheable As with caching the system BIOS above, enabling the Video BIOS cache will cause access to the video BOS addressed at C0000h to C7FFFFh to be cached. w 8/16 bit I/O Recovery Time The recovery time is the length of time measured in CPU clocks, which the system will delay after the completion of an I/O request. This delay takes place because the CPU is operationg so much faster than the I/O bus that the CPU must be delayed to allow for the completion of the I/O request. [. . . ] 6. 1 The Flash Memory Writer Utility Screen (Award) FLASH MEMORY WRITER V3. 0 Copyright (C) 1993, AWARD Software Inc. , For FX/HX-2A59CT51 Date:4/13/95 File Name to Program: Error Message: Type in the whole file name, e. g. The utility will then ` Blank' , ` Erase' and then ` , Program' the flash memory on the mainboard with the new BIOS file. You should choose "yes" to save the original system BIOS to a floppy diskette before you program the new BIOS. This leaves you with a backup of your original BIOS in case you need to reinstall it. [. . . ]